The invention relates to an integrated circuit layout device, a method thereof and a program thereof.
In designing the integrated circuit (e.g., an LSI (Large Scale Integration), an IC (Integrated Circuit), etc) a static timing analysis (Static Timing Analysis) has hitherto been carried out. The static timing analysis (which will hereinafter also be abbreviated to STA) is that a delay of a path is basically computed in total of maximum values or minimum values of delay values of signal propagation time of each of elements building up a logic circuit that connects one sequential circuit to another sequential circuit, and the timing analysis is thus performed. At the present, however, a scatter in the respective element (a manufacturing scatter) becomes relatively large as compared with a delay constraint value of the path. Then, it is difficult to make a design satisfying a timing constraint in the total of the maximum values (or the minimum values) of the respective elements. Hence, there is developed a statistical static timing analysis for obtaining a path delay distribution by plotting delay values of the respective element as a probability distribution and performing a statistical operation from the delay probability distribution of the respective elements on the path.
The statistical static timing analysis (which will hereinafter also be abbreviated to SSTA) enables acquisition of a yield of an integrated circuit that could not be acquired by the STA. Herein, the yield of the integrated circuit connotes a rate of the integrated circuits having an operating frequency exceeding a predetermined frequency. The SSTA has, however, a drawback of requiring a length of processing time and a memory that are several times as much as those of the STA. Hence, turn around time for a timing improvement, which repeatedly changes the design (such as a change in layout and a change in logic) for the timing improvement and evaluation of a yield of the integrated circuit by use of the SSTA, becomes longer than the turn around time for the timing improvement that employs the conventional STA.    [Patent document 1] Japanese Patent Application Laid-Open Publication No.2004-252831    [Patent document 2] Japanese Patent Application Laid-Open Publication No.2005-11892    [Patent document 3] Japanese Patent Application Laid-Open Publication No.2005-92885